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The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

机译:用于升级ALICE内部跟踪系统的ALPIDE像素传感器芯片

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摘要

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm2 for the application in the Inner Barrel Layers and below 20 mW/cm2 for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.
机译:ALPIDE芯片是CMOS单片有源像素传感器,正在开发中,用于升级CERN大型强子对撞机的ALICE实验的ITS。 ALPIDE芯片采用180 nm CMOS成像工艺实现,并制造在具有高电阻率外延层的基板上。它的尺寸为15mm×30mm,包含一个512×1024像素的矩阵,具有像素内放大,整形,判别和多事件缓冲功能。敏感矩阵的读数被命中驱动。如果没有命中值需要读出,并且功耗与占用率成正比,则矩阵上没有信令活动。该传感器满足以下实验要求:检测效率高于99%,假命中概率低于10-5且空间分辨率为5μm。提供了在100 kHz时读取Pb-Pb相互作用的功能。对于内桶层中的应用,ALPIDE芯片的功率密度预计将小于35 mW / cm2,对于占用率较低的外桶层,则将低于20 mW / cm2。该文稿描述了计划于2016年初提交的最终ALPIDE芯片的体系结构和主要功能。还报道了全尺寸原型前身的实验资格鉴定的早期结果。

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  • 作者

    Aglieri Rinella, Gianluca;

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  • 年度 2016
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  • 原文格式 PDF
  • 正文语种 eng
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